1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having self-aligned contact pads (SACs) and a method for manufacturing the same.
2. Description of the Related Art
As the integration density of semiconductor devices increases, gaps between adjacent devices disposed within the semiconductor devices decrease, and an area occupied by each of the semiconductor devices decreases. Accordingly, the area of a contact region continues to decrease, and contact margins also become reduced. Thus, alignment margins required in a photolithographic process become reduced. Recently, a method for manufacturing self-aligned contact pads in a highly integrated semiconductor device, which is capable of increasing alignment margins, has been suggested.
A conventional semiconductor device having self-aligned contact pads (SACs) and a method for manufacturing the same will be described with reference to FIGS. 1, 2, 3A, 3B, 4A, and 4B. FIGS. 1 and 2 are plan views illustrating a portion of a semiconductor device having SACS, where the semiconductor device is made using a conventional manufacturing method. FIGS. 3A and 3B are views illustrating a cross section of a semiconductor substrate taken along lines a-axe2x80x2 and b-bxe2x80x2, respectively, of FIG. 1. FIGS. 4A and 4B are views illustrating a cross section of a semiconductor substrate taken along lines a-axe2x80x2 and b-bxe2x80x2, respectively, of FIG. 2.
Referring to FIGS. 1, 3A, and 3B, an isolation layer 20 is formed to define active regions 15 on a semiconductor substrate 10. The active regions 15 each have a major axis and a minor axis. A plurality of gates 35 are formed on the semiconductor substrate 10 to cross the active regions 15 and extend in the direction of the minor axis of each of the active regions 15. Each of the gates 35 includes a stacked structure comprised of a gate insulating layer 22, a gate electrode 25, and a capping layer 27, and spacers 30 formed to surround the sidewalls of each of the stacked structures. Two gates 35 are disposed on each of the active regions 15. Here, the capping layer 27 and the spacers 30 are formed of a nitride layer which has a different etching selectivity from that of an interlayer insulating layer to be formed in a subsequent process.
Next, impurities are implanted into the active regions 15 at either side of each of the gates 35, thereby forming a first source/drain region 40a and a second source/drain region 40b. An interlayer insulating layer 45 is formed to completely fill a gap between adjacent gates 35, and then the top surface of the interlayer insulating layer 45 is planarized.
Next, photoresist patterns 50 used to form SACs are formed into an island shape on the interlayer insulating layer 45. The photoresist patterns 50 are formed to have the same size as the active regions 15 at rows where the active regions 15 are not formed.
Referring to FIGS. 2, 4A, and 4B, the interlayer insulating layer 45 is etched using the photoresist patterns 50 as etching masks so that first and second contact holes H11 and H12 are formed to expose the top surfaces of the first and second source/drain regions 40a and 40b, respectively. The photoresist patterns 50 are removed, and then a doped polysilicon layer is formed to completely fill the first and second contact holes H11 and H12. The top surfaces of the doped polysilicon layer and the interlayer insulating layer 45 are planarized to expose the top surface of the capping layer 27. Thus, first and second SACs 55a and 55b are formed to directly contact the top surfaces of the first and second source/drain regions 40a and 40b, respectively.
During the etching process for forming the first and second contact holes H11 and H12, an etching gas, such as C4F8 or C5F8, is used in order to make the interlayer insulating layer 45 have a high etching selectivity with respect to a nitride layer. However, during the etching process using such an etching gas, a considerable amount of polymer may be generated. If the aspect ratio of a contact hole is high, polymer generated during etching cannot be removed from the contact hole, and thus the etching process may be easily stopped. Accordingly, in order to prevent such a phenomenon, the interlayer insulating layer 45 is over-etched by increasing the etching time.
If the area occupied by the photoresist patterns 50 is small, the uppermost portion of the photoresist patterns 50 may be deformed during over-etching of the interlayer insulating layer 45. In addition, the photoresist patterns 50 may collapse because the photoresist patterns 50 formed into an island shape are weak. In particular, since the edge of each of the photoresist patterns 50 is thinly formed, adjacent first SACs 55a are not completely isolated from each other, and a bridge is generated between the adjacent first SACs 55a. 
The amount of etching gas required in etching is proportional to the area of material to be etched, and thus the etch rate of a contact hole having a large width is lower than the etch rate of a contact hole having a small width. If the photoresist patterns 50 are formed in an island shape, the first contact hole H11, in which the first SAC 55a will be formed, has a width smaller than the second contact hole H12, in which the second SAC 55b will be formed. Thus, the etching rate of the first contact hole H11 is different from the etching rate of the second contact hole H12. Accordingly, if the amount of etching gas is determined in consideration of the size of only one of the first and second contact holes H11 and H12, it is difficult to form the other contact hole in a desired shape.
To solve the above and other related problems of the prior art, there is provided a semiconductor device in which adjacent self-aligned contact pads (SACs) are completely isolated from one another. Moreover, there is provided a method for manufacturing a semiconductor device having SACs, that overcomes the prior art problem of irregular etching of the contact holes in which the SACs are formed due to different contact hole widths.
According to an aspect of the present invention, there is provided a semiconductor device that comprises a semiconductor substrate. An isolation layer is formed on the semiconductor substrate for defining a plurality of active regions. Each of the plurality of active regions has a major axis and a minor axis. A plurality of gates are formed to cross the plurality of active regions and extend in a direction of the minor axis of each of the plurality of active regions. Each of the plurality of gates has a first side and a second side that are opposing and that run along the direction of the minor axis. A plurality of first and second source/drain regions are formed in the plurality of active regions at either of the first side or the second side of each of the plurality of gates. Each of the plurality of first and second source/drain regions has a top surface. A plurality of first self-aligned contact pads (SACs) and a plurality of second SACs are formed to contact the top surface of each of the plurality of first and second source/drain regions, respectively.
According to another aspect of the present invention, each of the plurality of second SACs have sidewalls and a top surface. The isolation layer has a top surface. An arrangement of the plurality of second SACs forms a plurality of columns. An arrangement of the plurality of first SACs forms a plurality of first rows having a plurality of second rows disposed in an alternating arrangement there between. The semiconductor device further comprises a plurality of contact plugs and a plurality of bit lines. Each of the plurality of contact plugs has a top surface. Each of the plurality of contact plugs is formed to contact the sidewalls and a predetermined portion of the top surface of one of the plurality of second SACs and a portion of the top surface of the isolation layer that is positioned along a same one of the plurality of columns as the one of the plurality of the second SACs. Each of the plurality of bit lines is respectively formed along one of the plurality of second rows and extends in a direction of the major axis. The plurality of second rows correspond to areas having an absence of contact between any of the plurality of active regions and the top surface of any of the plurality of contact plugs.
According to yet another aspect of the present invention, the semiconductor device further comprises a plurality of third SACs. Each of the plurality of third SACs have sidewalls and a top surface, and are formed to respectively contact areas of the top surface of the isolation layer that are positioned along a same vertical axis as the plurality of first and second source/drain regions. Each of the plurality of contact plugs is formed to further contact the sidewalls and a predetermined portion of the top surface of one of the plurality of third SACs positioned at the same one of the plurality of columns as the one of the plurality of second SACs, respectively.
According to a further aspect of the present invention, there is provided a method for manufacturing a semiconductor device. An isolation layer is formed on a semiconductor substrate. The isolation layer defines a plurality of active regions. Each of the plurality of active regions has a major axis and a minor axis. A plurality of gates are formed on areas of the semiconductor substrate on which the isolation layer is formed. The plurality of gates are formed to cross the plurality of active regions and extend in a direction of the minor axis of each of the plurality of active regions. Each of the plurality of gates has a top surface, and a first side and a second side that are opposing and that that run along the direction of the minor axis. A plurality of first and second drain/source regions are formed in the plurality active regions at either of the first side or the second side of each of the plurality of gates. Each of the plurality of first and second source/drain regions has a top surface. A first interlayer insulating layer is formed on regions of the semiconductor substrate on which the plurality of first and second source/drain regions are formed. The first interlayer insulating layer is formed to completely fill spaces among the plurality of gates and to have a planarized top surface. Photoresist patterns are formed in a line shape at each of a plurality of rows where an absence exists of any formation of the plurality of active regions on the first interlayer insulating layer. The line shape extends in a direction of the major axis. The first interlayer insulating layer is etched using the photoresist patterns as etching masks to form a plurality of contact holes through which the top surface of each of the plurality of first and second source/drain regions are respectively exposed. The photoresist patterns are removed. A plurality of first self-aligned contact pads (SACS) and a plurality of second SACs are formed to respectively contact the top surface of each of the plurality of first and second source/drain regions and to be level with the top surface of each of the plurality of gates, by filling the plurality of contact holes with a conductive material.
According to a yet further aspect of the present invention, the method further comprises the step of forming a material layer that partially fills the spaces among the plurality of gates, subsequent to the step of forming the plurality of first and second source/drain regions. The material layer is formed of an insulating layer having a different etching selectivity from that of the first interlayer insulating layer and is etched along with the first interlayer insulating layer.
According to a yet still further aspect of the present invention, each of the plurality of the second SACs has sidewalls and a top surface, the isolation layer has a top surface, an arrangement of the plurality of second SACs forms a plurality of columns, and an arrangement of the plurality of first SACs forms a plurality of first rows having a plurality of second rows disposed in an alternating arrangement there between. The method further comprises the step of forming a second interlayer insulating layer on portions of the semiconductor substrate on which the plurality of first SACs and the plurality of second SACs are formed. A plurality of contact plugs are formed through the first and the second interlayer insulating layers to respectively contact the sidewalls and a predetermined portion of the top surface of each of the plurality of second SACs and a portion of the top surface of the isolation layer that is positioned along a same one of the plurality of columns as the one of the plurality of second SACs. A plurality of bit lines are formed. Each of the plurality of bit lines are respectively formed along one of the plurality of second rows and extend in a direction of the major axis of each of the plurality of active regions. The plurality of second rows correspond to areas having an absence of contact between any of the plurality of active regions and a top surface of any of the plurality of contact plugs.
According to an additional aspect of the present invention, the method further comprises the step of forming a plurality of third SACS to respectively contact the top surface of the isolation layer positioned along a same horizontal axis as the plurality of first and second source/drain regions. Each of the plurality of contact plugs is formed to further contact sidewalls and a predetermined portion of each of the plurality of third SACs positioned at the same column as the one of the plurality of second SACs.
According to a yet additional aspect of the present invention, each of the photoresist patterns are formed to include a protrusion covering the top surface of the isolation layer positioned each of a plurality of rows whereat the plurality of active regions are formed.
According to the present invention, it is possible to manufacture a semiconductor device in which adjacent self-aligned contact pads are completely isolated from one another. In addition, it is possible to solve the problem of the prior art in which contact holes, wherein self-aligned contact pads will be formed, are irregularly etched due to their different widths.